On Mon, 2007-06-25 at 18:46 -0700, Dan Williams wrote: > > Context switches on this platform flush the L1 cache so bouncing > between a workqueue and the MD thread is painful.
Why is context switches between two kernel threads flushing the L1 cache? Is this a flaw in the ARM arch? I would think the only thing that needs to be done between a context switch of two kernel threads (or even a user thread to a kernel thread) is update the general regs and stack. The memory access (page_tables or whatever ARM uses) should stay the same. Perhaps something else is at fault here. Thanks for testing! -- Steve - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
