> > Yes, that makes sense. > > But on the machine, I see IBRS bit set on all cores. As you said, > > someone else might be writing the MSR. I will try to find that out and will > update the patch accordingly. > > > > I initially suspected it to be __ssb_select_mitigation() as I have > > "spec_store_bypass_disable=on" in the kernel command line, but turns out > > it's > not so. > > I will update you more on this. > > There are lots of places like the firmware mitigation stuff and other things > which > write that MSR. And because the bit is set in x86_spec_ctrl_base it will be > on at > some point and stay so.
True! After a bit of experimenting with printk(), I see that it's being set by intel_set_ssb_state() during systemd initialization. > > Writing it explicitely at the point where it is set makes it independent of > other > mechanisms which touch that MSR and Just Works. Yes, that makes sense. I will add an explicit wrmsrl(). Just wanted to have a better understanding of how things work. Regards, Sai
