Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.

For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.

Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 3 ++-
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 3 ++-
 arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi 
b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index d63b56e..5640dac 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -571,7 +571,8 @@
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi 
b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 0298bd0..a8964c0 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -626,7 +626,8 @@
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi 
b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 2a4cf42..fd2bcd4 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -455,7 +455,8 @@
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
-- 
2.7.4

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