We recently made enabling LPIs a lot stricter, by checking that
they are disabled before we enable them. By doing so, we missed
the CPU hotplug case altogether, where we leave LPIs enabled
on hotplug off (we expect the CPU to eventually come back),
and won't write a different value anyway on hotplug on.
So let's skip that check if we detect that particular case.
Fixes: 6eb486b66a30 ("irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed
before enabling")
Reported-by: Sumit Garg <sumit.g...@linaro.org>
Tested-by: Sumit Garg <sumit.g...@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 0269ffb93f6e..d7842d312d3e 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3427,6 +3427,16 @@ static int redist_disable_lpis(void)
u64 timeout = USEC_PER_SEC;
u64 val;
+ /*
+ * If coming via a CPU hotplug event, we don't need to disable
+ * LPIs before trying to re-enable them. They are already
+ * configured and all is well in the world. Detect this case
+ * by checking the allocation of the pending table for the
+ * current CPU.
+ */
+ if (gic_data_rdist()->pend_page)
+ return 0;
+
if (!gic_rdists_supports_plpis()) {
pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
return -ENXIO;
--
2.17.1
