Quoting Chris Packham (2018-05-23 22:23:41)
> The correct fieldbit value for the NAND PLL reload trigger is 27.
>
> Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
> ---Applied to clk-next
