On Fri, May 18, 2018 at 11:38:27AM +0300, Jarkko Nikula wrote:
> Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C
> than Sunrisepoint which uses 120 MHz. Preliminary information was that
> both share the same clock rate but actual silicon implements elevated
> rate for better support for 3.4 MHz high-speed I2C.
>
> This incorrect input clock rate results too high I2C bus clock in case
> ACPI doesn't provide tuned I2C timing parameters since I2C host
> controller driver calculates them from input clock rate.
>
> Fix this by using the correct rate. We still share the same 230 ns SDA
> hold time value than Sunrisepoint.
>
> Cc: sta...@vger.kernel.org
> Fixes: b418bbff36dd ("mfd: intel-lpss: Add Intel Cannonlake PCI IDs")
> Reported-by: Jian-Hong Pan <jian-h...@endlessm.com>
> Reported-by: Chris Chiu <c...@endlessm.com>
> Reported-by: Daniel Drake <dr...@endlessm.com>
> Signed-off-by: Jarkko Nikula <jarkko.nik...@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
