On Fri, May 18, 2018 at 11:38:27AM +0300, Jarkko Nikula wrote: > Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C > than Sunrisepoint which uses 120 MHz. Preliminary information was that > both share the same clock rate but actual silicon implements elevated > rate for better support for 3.4 MHz high-speed I2C. > > This incorrect input clock rate results too high I2C bus clock in case > ACPI doesn't provide tuned I2C timing parameters since I2C host > controller driver calculates them from input clock rate. > > Fix this by using the correct rate. We still share the same 230 ns SDA > hold time value than Sunrisepoint. > > Cc: [email protected] > Fixes: b418bbff36dd ("mfd: intel-lpss: Add Intel Cannonlake PCI IDs") > Reported-by: Jian-Hong Pan <[email protected]> > Reported-by: Chris Chiu <[email protected]> > Reported-by: Daniel Drake <[email protected]> > Signed-off-by: Jarkko Nikula <[email protected]>
Acked-by: Mika Westerberg <[email protected]>
