On Wed, Apr 11, 2018 at 10:08:06AM +0200, Boris Brezillon wrote:
> On Wed, 11 Apr 2018 09:36:56 +0200
> Ladislav Michl <la...@linux-mips.org> wrote:
>
> > Hi Boris,
> >
> > On Wed, Apr 11, 2018 at 09:15:28AM +0200, Boris Brezillon wrote:
[...]
> > > Not sure this approach is safe on all archs: if the cache is VIVT or
> > > VIPT, you may have several entries pointing to the same phys page, and
> > > then, when dma_map_page() does its cache maintenance operations, it's
> > > only taking one of these entries into account.
> >
> > Hmm, I used the same approach Samsung OneNAND driver does since commit
> > dcf08227e964a53a2cb39130b74842c7dcb6adde.
> > Both TI OMAP3630 and Samsung S5PC110 are using Cortex-A8 which
> > is VIPT. In that case samsung's driver code has the same problem.
> >
> > > In other parts of the MTD subsystem, we tend to not do DMA on buffers
> > > that have been vmalloc-ed.
> > >
> > > You can do something like
> > >
> > > if (virt_addr_valid(buf))
> > > /* Use DMA */
> > > else
> > > /*
> > > * Do not use DMA, or use a bounce buffer
> > > * allocated with kmalloc
> > > */
> >
> > Okay, I'll use this approach then, but first I'd like to be sure above is
> > correct. Anyone?
>
> See this discussion [1]. The problem came up a few times already, so
> might find other threads describing why it's not safe.
>
> [1]https://lists.linuxfoundation.org/pipermail/iommu/2016-March/016240.html
Question was more likely whenever there might exist more that one mapping
of the same page. But okay, I'll disable DMA for highmem. Patch will follow.
ladis
