[PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4

[Kunihiko Hayashi]

Pro4 SoC has clock lines for Giga-bit feature and ethernet phy,
and these are mandatory to activate the ethernet controller. This adds
support for the clock lines.

Signed-off-by: Kunihiko Hayashi <hayashi.kunih...@socionext.com>
---
 drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c 
b/drivers/clk/uniphier/clk-uniphier-sys.c
index 7d66dfb..ebc78ab2 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -102,13 +102,16 @@ const struct uniphier_clk_data 
uniphier_pro4_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),        /* 288 MHz */
        UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125),     /* 589.824 MHz 
*/
        UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
+       UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1),          /* 250 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
        UNIPHIER_LD4_SYS_CLK_NAND(2),
        UNIPHIER_LD4_SYS_CLK_SD,
        UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
        UNIPHIER_PRO4_SYS_CLK_ETHER(6),
+       UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* HSC, MIO, RLE */
+       UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
        UNIPHIER_PRO4_SYS_CLK_GIO(12),                  /* Ether, SATA, USB3 */
        UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
        UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
-- 
2.7.4