> -----Original Message----- > From: Borislav Petkov <b...@alien8.de> > Sent: Wednesday, March 28, 2018 11:44 AM > To: Ghannam, Yazen <yazen.ghan...@amd.com> > Cc: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/3] EDAC/amd64: Print ECC enabled/disabled for nodes > with enabled MCs > > On Wed, Mar 28, 2018 at 02:38:11PM +0000, Ghannam, Yazen wrote: > > In either of those cases we won't get to debug_display_dimm_sizes* > > because we won't initialize the instance. > > So you move that code which accesses csrows up so that it has the > required information to query DIMM state/presence. >
I don't think we need to look at the csrows. We just need to check if the controller is enabled or not. A controller is enabled if there is a DIMM behind it and disabled if there isn't. > > /* Assume UMC MCA banks are enabled. */ > > nb_mce_en = true; > > Also, I don't like that assumption. > I'll look into it. > > This would work for Fam17h. For older systems I think we can look at > > D18F2x94_dct[1:0][DisDramInterface] > > > > Or maybe we have a separate function to check for enabled memory > controllers > > before we check for ECC? > > The best would be to have a function which checks whether DIMMs are > present on the node and act accordingly. You can pull up some of the > work of caching registers which are used in debug_display_dimm_sizes* > and use that info to get the required DIMM state upfront. > Okay, so I'll do a separate function. Thanks, Yazen
