From: Yazen Ghannam <yazen.ghan...@amd.com>
Set the DIMM device type for Fam17h.
Cc: <sta...@vger.kernel.org> # 4.14.x
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
---
drivers/edac/amd64_edac.c | 17 ++++++++++++++---
drivers/edac/amd64_edac.h | 1 +
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 054086b19c6c..59d0085e4ffa 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -998,7 +998,7 @@ static void read_dct_base_mask(struct amd64_pvt *pvt)
static void determine_memory_type(struct amd64_pvt *pvt)
{
- u32 dram_ctrl, dcsm;
+ u32 dram_ctrl, dcsm, dimm_cfg;
switch (pvt->fam) {
case 0xf:
@@ -1046,12 +1046,22 @@ static void determine_memory_type(struct amd64_pvt *pvt)
goto ddr3;
case 0x17:
- if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
+ dimm_cfg = pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg;
+
+ if (dimm_cfg & BIT(5))
pvt->dram_type = MEM_LRDDR4;
- else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
+ else if (dimm_cfg & BIT(4))
pvt->dram_type = MEM_RDDR4;
else
pvt->dram_type = MEM_DDR4;
+
+ if (dimm_cfg & BIT(7))
+ pvt->dev_type = DEV_X16;
+ else if (dimm_cfg & BIT(6))
+ pvt->dev_type = DEV_X4;
+ else
+ pvt->dev_type = DEV_UNKNOWN;
+
return;
default:
@@ -2855,6 +2865,7 @@ static int init_csrows(struct mem_ctl_info *mci)
for (j = 0; j < pvt->channel_count; j++) {
dimm = csrow->channels[j]->dimm;
dimm->mtype = pvt->dram_type;
+ dimm->dtype = pvt->dev_type;
dimm->edac_mode = edac_mode;
}
}
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 1d4b74e9a037..47696d3ce487 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -368,6 +368,7 @@ struct amd64_pvt {
/* cache the dram_type */
enum mem_type dram_type;
+ enum dev_type dev_type;
struct amd64_umc *umc; /* UMC registers */
};
--
2.14.1
