On Fri, Mar 09, 2018 at 11:14:42AM +0100, Paul Kocialkowski wrote:
> From: Florent Revest <florent.rev...@free-electrons.com>
> 
> Device Tree bindings for the Allwinner's video engine
> 
> Signed-off-by: Florent Revest <florent.rev...@free-electrons.com>
> ---
>  .../devicetree/bindings/media/sunxi-cedrus.txt     | 44 
> ++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/sunxi-cedrus.txt
> 
> diff --git a/Documentation/devicetree/bindings/media/sunxi-cedrus.txt 
> b/Documentation/devicetree/bindings/media/sunxi-cedrus.txt
> new file mode 100644
> index 000000000000..138581113c49
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/sunxi-cedrus.txt
> @@ -0,0 +1,44 @@
> +Device-Tree bindings for SUNXI video engine found in sunXi SoC family
> +
> +Required properties:
> +- compatible     : "allwinner,sun4i-a10-video-engine";
> +- memory-region     : DMA pool for buffers allocation;
> +- clocks         : list of clock specifiers, corresponding to
> +                   entries in clock-names property;
> +- clock-names            : should contain "ahb", "mod" and "ram" entries;
> +- resets         : phandle for reset;
> +- interrupts     : should contain VE interrupt number;
> +- reg                    : should contain register base and length of VE.
> +
> +Example:
> +
> +reserved-memory {
> +     #address-cells = <1>;
> +     #size-cells = <1>;
> +     ranges;
> +
> +     ve_reserved: cma {
> +             compatible = "shared-dma-pool";
> +             reg = <0x43d00000 0x9000000>;
> +             no-map;
> +             linux,cma-default;
> +     };
> +};
> +
> +video-engine {
> +     compatible = "allwinner,sun4i-a10-video-engine";
> +     memory-region = <&ve_reserved>;
> +
> +     clocks = <&ahb_gates 32>, <&ccu CLK_VE>,
> +              <&dram_gates 0>;

This should be updated to sunxi-ng clocks:

clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_DRAM_VE>;

> +     clock-names = "ahb", "mod", "ram";
> +
> +     assigned-clocks = <&ccu CLK_VE>;
> +     assigned-clock-rates = <320000000>;
> +
> +     resets = <&ccu RST_VE>;
> +
> +     interrupts = <53>;
> +
> +     reg = <0x01c0e000 4096>;
> +};
> -- 
> 2.16.2
> 
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