From: Grant Grundler <[EMAIL PROTECTED]> Date: Sat, 26 May 2007 18:16:31 -0600
> Are they really? The device is generating the transaction on the bus. > The PCI host controller (in general) will be routing that transaction > to wherever the "dest addr" of the MSI lives. It doesn't have to be > in the CPU but it will certainly be a proxy for that CPU if it's not. > We won't care if the proxy only have one IRQ line going to the CPU > as long as the de-muxing of the "data" portion results in a unique > identifier that can be mapped to exactly one interrupt handler. True, on sparc64 PCI-E controllers, for example, the MSI vector is received by the PCI-E host controller, and the host controller turns this into a cpu format interrupt packet for the system bus. I guess on IRQ pin starved systems, the PCI-E host controller or something similar would get interrogated by the cpu for the MSI vector number. I don't want to be the person who has to code up support for that, as it's not easy to shim mid-level vectoring into the generic IRQ layer currently. I'd love to be able to do that on sparc64 instead of what arch/sparc64/kernel/pci_sun4v.c's pci_sun4v_msi_prehandler() is doing. There is a lot of information and vectoring capabilities present that I'm simply not taking advantage of yet :-) - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
