Microcode updates can be safer if the caches are clean.
Some of the issues around in certain Broadwell parts
can be addressed by doing a full cache flush.
Signed-off-by: Ashok Raj <ashok....@intel.com>
Cc: X86 ML <x...@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Ingo Molnar <mi...@kernel.org>
Cc: Tony Luck <tony.l...@intel.com>
Cc: Andi Kleen <andi.kl...@intel.com>
Cc: Boris Petkov <b...@suse.de>
Cc: Tom Lendacky <thomas.lenda...@amd.com>
Cc: Arjan Van De Ven <arjan.van.de....@intel.com>
---
arch/x86/kernel/cpu/microcode/intel.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/kernel/cpu/microcode/intel.c
b/arch/x86/kernel/cpu/microcode/intel.c
index 137c9f5..50e48c4 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -601,6 +601,13 @@ static int apply_microcode_early(struct ucode_cpu_info
*uci, bool early)
return UCODE_OK;
}
+ /*
+ * Microcode updates can be safer if the caches are clean.
+ * Some of the issues around in certain Broadwell parts
+ * can be addressed by doing a full cache flush.
+ */
+ native_wbinvd();
+
/* write microcode via MSR 0x79 */
native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -817,6 +824,13 @@ static enum ucode_state apply_microcode_intel(int cpu)
return UCODE_OK;
}
+ /*
+ * Microcode updates can be safer if the caches are clean.
+ * Some of the issues around in certain Broadwell parts
+ * can be addressed by doing a full cache flush.
+ */
+ wbinvd();
+
/* write microcode via MSR 0x79 */
wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
--
2.7.4
