On Thu, Feb 01, 2018 at 10:59:44PM +0100, KarimAllah Ahmed wrote: > Intel processors use MSR_IA32_ARCH_CAPABILITIES MSR to indicate RDCL_NO > (bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default the > contents will come directly from the hardware, but user-space can still > override it. > > [dwmw2: The bit in kvm_cpuid_7_0_edx_x86_features can be unconditional] > > Cc: Asit Mallick <asit.k.mall...@intel.com> > Cc: Dave Hansen <dave.han...@intel.com> > Cc: Arjan Van De Ven <arjan.van.de....@intel.com> > Cc: Tim Chen <tim.c.c...@linux.intel.com> > Cc: Linus Torvalds <torva...@linux-foundation.org> > Cc: Andrea Arcangeli <aarca...@redhat.com> > Cc: Andi Kleen <a...@linux.intel.com> > Cc: Thomas Gleixner <t...@linutronix.de> > Cc: Dan Williams <dan.j.willi...@intel.com> > Cc: Jun Nakajima <jun.nakaj...@intel.com> > Cc: Andy Lutomirski <l...@kernel.org> > Cc: Greg KH <gre...@linuxfoundation.org> > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Ashok Raj <ashok....@intel.com> > Reviewed-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.w...@oracle.com>
