* Dan Williams <dan.j.willi...@intel.com> wrote:
> > The flip side is that if the MFENCE stalls the STAC that is ahead of it
> > could be
> > processed for 'free' - while it's always post barrier with my suggestion.
>
> This 'for free' aspect is what I aiming for.
Ok.
> >
> > But in any case it would be nice to see a discussion of this aspect in the
> > changelog, even if the patch does not change.
>
> I'll add a note to the changelog that having the fence after the
> 'stac' hopefully allows some overlap of the cost of 'stac' and the
> flushing of the instruction pipeline.
Perfect!
Thanks,
Ingo
