On Mon, 15 Jan 2018 09:35:45 +0800 TimGuo <tim...@zhaoxin.com> wrote:
> Centaur CPU has a constant frequency TSC and that TSC does not stop in > C-States. > But because the flags are not set for that CPU, the TSC is treated as non > constant > frequency and assumed to stop in C-States, which makes it an unreliable and > unusable > clock source. Setting those flags tells the kernel that the TSC is usable, so > it > will select it over HPET. The effect of this is that reading time stamps > (from kernel > or userspace) will be faster and more efficient. And this is true for all processors back to IDT WinChip ? Alan
