On Thu, Jan 04, 2018 at 09:56:44AM -0800, Tim Chen wrote: > Set IBRS upon kernel entrance via syscall and interrupts. Clear it > upon exit.
So not only did we add a CR3 write, we're now adding an MSR write to the entry/exit paths. Please tell me that these are 'fast' MSRs? Given people are already reporting stupid numbers with just the existing PTI/CR3, what kind of pain are we going to get from adding this? > If NMI runs when exiting kernel between IBRS_DISABLE and > SWAPGS, the NMI would have turned on IBRS bit 0 and then it would have > left enabled when exiting the NMI. IBRS bit 0 would then be left > enabled in userland until the next enter kernel. > > That is a minor inefficiency only, but we can eliminate it by saving > the MSR when entering the NMI in save_paranoid and restoring it when > exiting the NMI. > > Signed-off-by: Andrea Arcangeli <aarca...@redhat.com> > Signed-off-by: Tim Chen <tim.c.c...@linux.intel.com> Invalid SoB chain, either you lost a From: Andrea or you need something else.
