On 12/22, Joel Stanley wrote: > The majority of the clocks in the system are gates paired with a reset > controller that holds the IP in reset. > > This borrows from clk_hw_register_gate, but registers two 'gates', one > to control the clock enable register and the other to control the reset > IP. This allows us to enforce the ordering: > > 1. Place IP in reset > 2. Enable clock > 3. Delay > 4. Release reset > > There are some gates that do not have an associated reset; these are > handled by using -1 as the index for the reset. > > Reviewed-by: Andrew Jeffery <and...@aj.id.au> > Signed-off-by: Joel Stanley <j...@jms.id.au> > ---
Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
