On Tue, 19 Dec 2017 16:15:41 -0600 Gary R Hook <gary.h...@amd.com> wrote:
> The AMD IOMMU specification Rev 3.00 (December 2016) introduces a > new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register > offset 0030h (IOMMU Extended Feature Register). > > When EPHSup=1, the IOMMU hardware requires the PPR bit of the > device table entry (DTE) to be set in order to support PPR for a > particular endpoint device. > > Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for > this revision of the AMD IOMMU specification. > > Signed-off-by: Gary R Hook <gary.h...@amd.com> > --- > 0 files changed Hmm, something funky there, but looks fine otherwise. Applied to v4.16-iommu/amd. Thanks, Alex
