We've documented this one already, but we didn't add it to the DTSI yet.

Suggested-by: Nickey Yang <nickey.y...@rock-chips.com>
Signed-off-by: Brian Norris <briannor...@chromium.org>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c6dae25a3f23..8940a3dc3670 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1648,6 +1648,8 @@
                         <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
                clock-names = "ref", "pclk", "phy_cfg", "grf";
                power-domains = <&power RK3399_PD_VIO>;
+               resets = <&cru SRST_P_MIPI_DSI0>;
+               reset-names = "apb";
                rockchip,grf = <&grf>;
                status = "disabled";
 
-- 
2.15.0.531.g2ccb3012c9-goog

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