On Sat, Nov 25, 2017 at 10:05:48AM +0800, Xie XiuQi wrote:
> In Intel SDM Volume 3B (253669-063US, July 2017), SRAO could be
> reported either via MCE or CMC:
>
> In cases when SRAO is signaled via CMCI the error signature is
> indicated via UC=1, PCC=0, S=0.
>
> Type(*1) UC EN PCC S AR Signaling
> ---------------------------------------------------------------
> UC 1 1 1 x x MCE
> SRAR 1 1 0 1 1 MCE
> SRAO 1 x(*2) 0 x(*2) 0 MCE/CMC
> UCNA 1 x 0 0 0 CMC
> CE 0 x x x x CMC
>
> NOTES:
> 1. SRAR, SRAO and UCNA errors are supported by the processor only
> when IA32_MCG_CAP[24] (MCG_SER_P) is set.
> 2. EN=1, S=1 when signaled via MCE. EN=x, S=0 when signaled via CMC.
>
> And there is a description in 15.6.2 UCR Error Reporting and Logging, for bit
> S:
>
> S (Signaling) flag, bit 56 - Indicates (when set) that a machine check
> exception was generated for the UCR error reported in this MC bank...
> When the S flag in the IA32_MCi_STATUS register is clear, this UCR error
> was not signaled via a machine check exception and instead was reported
> as a corrected machine check (CMC).
>
> So we could merge this two case, and just remove the S=0 check for SRAO
> in mce_severity().
>
> ---
> v2: add OVER=0 check and merge MCE and CMC case.
>
> Signed-off-by: Xie XiuQi <[email protected]>
> Tested-by: Chen Wei <[email protected]>
> Reviewed-by: Tony Luck <[email protected]>
> ---
> arch/x86/kernel/cpu/mcheck/mce-severity.c | 26 +++++++++++++++++---------
> 1 file changed, 17 insertions(+), 9 deletions(-)
Applied, thanks.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
