On Tue, 2007-05-08 at 02:39 -0700, Chris Wright wrote:
> OK, looks very similar all things considered. One thing I didn't do
> was fix lapic timer calibration (was hoping you'd do that part, and you
> did ;-) I've noticed that something has changed and I'm seeing irq0
> handled on cpu3 (4 cpu system), where it used to be on cpu0 as expected.
Strange, irq balancing ?
> In addition lapic timer is firing there, and I'm seeing a higher
> interrupt load than I used to. This is the same in your set and mine.
Is irq0 _and_ the lapic timer firing ?
tglx
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