Since commit dfea747d2aba ("drivers: base: cacheinfo: support DT
overrides for cache properties"), we can set the correct cacheinfo
via DT. But the cache type can't be set in the same way.
I found this may be a problem in recent tests. I tested L3 cache
node setting in DT in Hisilicon D03/D05 board. And I got cacheinfo
via sysfs below:
$ cat /sys/devices/system/cpu/cpu*/cache/index3/
allocation_policy level power/
shared_cpu_map uevent write_policy
coherency_line_size number_of_sets shared_cpu_list
size ways_of_associativity
This is incomplete, no type file to display type info. Because L3
cache is uncore, we can't get correct type info from system
register, and will get a default type "CACHE_TYPE_NOCACHE". Then
use "lscpu" will print an error like below:
$ lscpu
lscpu: cannot open /sys/devices/system/cpu/cpu0/cache/index3/type:
No such file or directory
So I think maybe we can set correct cache type via DT too.
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
---
drivers/base/cacheinfo.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index eb3af27..3e650dc 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -122,6 +122,15 @@ static inline int get_cacheinfo_idx(enum cache_type type)
return type;
}
+static void cache_type(struct cacheinfo *this_leaf)
+{
+ const __be32 *cache_type;
+
+ cache_type = of_get_property(this_leaf->of_node, "type", NULL);
+ if (cache_type)
+ this_leaf->type = of_read_number(cache_type, 1);
+}
+
static void cache_size(struct cacheinfo *this_leaf)
{
const char *propname;
@@ -194,6 +203,7 @@ static void cache_of_override_properties(unsigned int cpu)
for (index = 0; index < cache_leaves(cpu); index++) {
this_leaf = this_cpu_ci->info_list + index;
+ cache_type(this_leaf);
cache_size(this_leaf);
cache_get_line_size(this_leaf);
cache_nr_sets(this_leaf);
--
2.7.4
