Hi Mathieu, On Tue, Aug 29, 2017 at 11:55 AM, Mathieu Desnoyers <mathieu.desnoy...@efficios.com> wrote: > ----- On Aug 28, 2017, at 1:12 PM, Max Filippov jcmvb...@gmail.com wrote: >> On Mon, Aug 28, 2017 at 12:36 AM, Mathieu Desnoyers >> <mathieu.desnoy...@efficios.com> wrote: >>> The membarrier system call now requires all architectures to implement >>> sync_core(). On Xtensa, it is provided by the EXTW instruction. >>> >>> [ Completely untested! Can someone on the xtensa side confirm whether >>> EXTW is the right way to serialize core execution and try it out ? ] >> >> Thanks for the patch. I'm currently travelling, I'll give it a try next week >> once I'm back at work. > > I think we may need to flush the icache to make it consistent with the dcache > too on xtensa, in addition to the EXTW. The goal here is to allow JIT engines > to reclaim and re-use memory after they discard dynamically generated code. > This is similar to what we'd need to do on arm32, where they have inconsistent > d/i-caches.
my understanding is that to support JIT engines on xtensa we need to do icache/dcache synchronization, this procedure is covered in the ISYNC instruction description in the ISA book, it involves MEMW and ISYNC, but not EXTW. EXTW is meant to work as a CPU barrier that orders all externally visible CPU signals, which seems unnecessary. Interestingly, currently we don't have MEMW between dcache flush and icache invalidation, so I need to add it to be consistent with the documented procedure. Then I believe that sync_core implementation should invoke flush_dcache_all followed by MEMW followed by invalidate_icache_all. Does that sound right? -- Thanks. -- Max
