Hi Andrei,
* Andrei Vagin <ava...@virtuozzo.com> wrote:
> Hi Thomas,
>
> We run CRIU tests for linux-next and today they detected an issue. I've
> bisected this problem and it looks like a problem is in this patch.
Ok, there appears to be a bug in that conversion - does the patch below fix the
regression for you?
Thanks,
Ingo
================================>
Subject: x86/idt: Fix the X86_TRAP_BP gate
From: Ingo Molnar <mi...@kernel.org>
Andrei Vagin reported a CRIU regression and bisected it back to:
90f6225fba0c ("x86/idt: Move IST stack based traps to table init")
This table init conversion loses the system-gate property of X86_TRAP_BP
and erroneously moves it from DPL3 to DPL0.
Fix it.
Reported-by: Andrei Vagin <ava...@virtuozzo.com>
Cc: Linus Torvalds <torva...@linux-foundation.org>
Cc: Peter Zijlstra <pet...@infradead.org>
Cc: Thomas Gleixner <t...@linutronix.de>
Signed-off-by: Ingo Molnar <mi...@kernel.org>
---
arch/x86/kernel/idt.c | 6 +++++-
arch/x86/kernel/idt.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
Index: tip/arch/x86/kernel/idt.c
===================================================================
--- tip.orig/arch/x86/kernel/idt.c
+++ tip/arch/x86/kernel/idt.c
@@ -44,6 +44,10 @@ struct idt_data {
#define ISTG(_vector, _addr, _ist) \
G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
+/* System interrupt gate with interrupt stack */
+#define SISTG(_vector, _addr, _ist) \
+ G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
+
/* Task gate */
#define TSKG(_vector, _gdt) \
G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
@@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] _
static const __initdata struct idt_data ist_idts[] = {
ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
- ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
+ SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
#ifdef CONFIG_X86_MCE
ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
