On 08/21/2017 03:42 PM, Peter Zijlstra wrote: > On Mon, Aug 21, 2017 at 09:25:50PM +0200, Peter Zijlstra wrote: >> On Mon, Aug 21, 2017 at 07:00:02PM +0100, Will Deacon wrote: >>>> No, I meant _from_ the LL load, not _to_ a later load. >>> Sorry, I'm still not following enough to give you a definitive answer on >>> that. Could you give an example, please? These sequences usually run in >>> a loop, so the conditional branch back (based on the status flag) is where >>> the read-after-read comes in. >>> >>> Any control dependencies from the loaded data exist regardless of the status >>> flag. >> Basically what Waiman ended up doing, something like: >> >> if (cmpxchg_relaxed(&pn->state, vcpu_halted, vcpu_hashed) != >> vcpu_halted) >> return; >> >> WRITE_ONCE(l->locked, _Q_SLOW_VAL); >> >> Where the STORE depends on the LL value being 'complete'. >>
pn->state == vcpu_halted is the prerequisite of putting _Q_SLOW_VAL into the lock. The order of writing vcpu_hashed into pn->state doesn't really matter. The cmpxchg_relaxed() here should synchronize with the cmpxchg() in pv_wait_node(). Cheers, Longman
