Alan Cox wrote:
>> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
>> index 72c286e..a128717 100644
>> --- a/drivers/ata/ahci.c
>> +++ b/drivers/ata/ahci.c
>> @@ -1369,10 +1369,14 @@ static unsigned int ahci_qc_issue(struct
>> ata_queued_cmd *qc)
>>
>> static void ahci_freeze(struct ata_port *ap)
>> {
>> + void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
>> void __iomem *port_mmio = ahci_port_base(ap);
>>
>> /* turn IRQ off */
>> writel(0, port_mmio + PORT_IRQ_MASK);
>> +
>> + /* clear IRQ pending bit */
>> + writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
>> }
>>
>
> Actually now I think about it the problem is even worse. On older systems
> IRQ delivery for SMP machines is asynchronous. So the following can occur
>
>
> device raises IRQ line
> IRQ request hits APIC bus
>
> We write IRQ off
> We clear IRQ pending
>
> We read back to ensure the write took
>
>
> IRQ arrives on CPU APIC
>
> (and yes this happens on dual P3 boxes - NE2K has some fantastic bugs at
> one point due to this)
I think the second patch should work regardless of IRQ posting. No?
--
tejun
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