On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng <icen...@aosc.io> wrote:
> The pin controller of H5 has three IRQs at the chip's GIC, which
> represents three banks of pinctrl IRQs. However, the device tree used to
> miss the third IRQ of the pin controller, which makes the PG bank IRQ
> not usable.
>
> Add the missing IRQ to the pinctrl node.
>
> Fixes: 4e36de179f27 ("arm64: allwinner: h5: add Allwinner H5 .dtsi")
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>Applied as fixes for 4.13. ChenYu
