On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <ste...@agner.ch> wrote: > The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT > and NAND_CLK_ROOT. However, the gate has been in the chain of the > latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT > only, e.g. as required by APBH-Bridge-DMA. > > Add new clocks which represent the clock after the gate, and use a > shared clock gate to correctly model the hardware. > > Signed-off-by: Stefan Agner <ste...@agner.ch>
Tested-by: Fabio Estevam <fabio.este...@nxp.com>
