This adds the bindings documentation for a basic single-register reset
controller.
The bindings describe a single 32-bit register that contains up to 32
reset lines, each deasserted by clearing the appropriate bit in the
register.
Signed-off-by: Joel Stanley <j...@jms.id.au>
---
.../devicetree/bindings/reset/reset-basic.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/reset-basic.txt
diff --git a/Documentation/devicetree/bindings/reset/reset-basic.txt
b/Documentation/devicetree/bindings/reset/reset-basic.txt
new file mode 100644
index 000000000000..7341e04e7904
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/reset-basic.txt
@@ -0,0 +1,31 @@
+Basic single-register reset controller
+======================================
+
+This describes a generic reset controller where the reset lines are controlled
+by single bits within a 32-bit memory location. The memory location is assumed
+to be part of a syscon regmap.
+
+Reset controller required properties:
+ - compatible: should be "reset-basic"
+ - #reset-cells: must be set to 1
+ - reg: reset register location within regmap
+
+Device node required properties:
+ - resets phandle
+ - bit number, counting from zero, for the desired reset line. Max is 31.
+
+Example:
+
+syscon {
+ compatible = "syscon";
+
+ uart_rest: rest@0c {
+ compatible = "reset-basic";
+ #reset-cells = <1>;
+ reg = <0x0c>;
+ };
+}
+
+&uart {
+ resets = <&uart_rest 0x04>;
+}
--
2.11.0
