* Mikulas Patocka <mpato...@redhat.com> wrote:
> On Tue, 16 May 2017, H. Peter Anvin wrote:
>
> > On 04/18/17 12:07, Mikulas Patocka wrote:
> > >
> > > However, on AMD K6-3 CPU, the processor initialization code never calls
> > > pat_init() and so __pat_enabled stays 1 and the function pat_enabled()
> > > returns true, even though the K6-3 CPU doesn't support PAT.
> > >
> >
> > OK, now I'm wondering: are you actually *using* said K6-3 machine, and
>
> I use it for playing music, browsing with the links browser and connecting
> to other machines with ssh. That machine is slow but it is completely
> quiet.
>
> It is also good to run my own software on a slow CPU to make sure that
> there are no obvious inefficiencies.
>
> > if so, are you actually dependent on write combining on it? The reason
>
> Those K6-3 MTRRs improve framebuffer write throughput by 33%.
>
> > I'm asking is because I would personally like to completely remove the
> > support for using MTRRs to create WC mappings, as it only affects a
> > handful of ancient CPUs: Pentium Pro, Pentium II, K6-*, and possibly
> > some Cyrix/Centaur part. Earlier CPUs didn't have WC, but could set WB,
> > WT or UC via the page tables without needing the PAT MSR, and newer CPUs
> > have PAT.
>
> MTRRs are also needed on Pentium 3, Core Solo and Core Duo due to an
> erratum that makes it not possible to set WC with PAT. See the comment
> before "clear_cpu_cap(c, X86_FEATURE_PAT)" in early_init_intel().
Ok, I'm inclined to apply your regression fix - hpa do you concur?
Thanks,
Ingo
