Hi Alexandre, > -----Original Message----- > From: Alexandre Belloni [mailto:[email protected]] > Sent: 2017年5月15日 17:44 > To: Wenyou Yang - A41535 <[email protected]> > Cc: Nicolas Ferre - M43238 <[email protected]>; Rob Herring > <[email protected]>; Pawel Moll <[email protected]>; Mark Rutland > <[email protected]>; Ian Campbell <[email protected]>; Kumar > Gala <[email protected]>; Russell King <[email protected]>; linux- > [email protected]; [email protected]; Oliver Hartkopp > <[email protected]>; [email protected]; Quentin Schulz > <[email protected]>; Wenyou Yang - A41535 > <[email protected]>; [email protected] > Subject: Re: [PATCH v3] ARM: dts: at91: sama5d2: add m_can nodes > > On 24/04/2017 at 09:12:17 +0800, Wenyou Yang wrote: > > Add nodes to support the Controller Area Network(M_CAN) on SAMA5D2. > > The version of M_CAN IP core is 3.1.0 (CREL = 0x31040730). > > > > As said in SAMA5D2 datasheet, the CAN clock is recommended to use > > frequencies of 20, 40 or 80 MHz. To achieve these frequencies, PMC > > GCLK3 must select the UPLLCK(480 MHz) as source clock and divide by > > 24, 12, or 6. So, the "assigned-clock-rates" property has three > > options: 20000000, 40000000, and 80000000. > > The "assigned-clock-parents" property should be referred to utmi > > fixedly. > > > > The MSBs [bits 31:16] of the CAN Message RAM for CAN0 and CAN1 are > > default configured in 0x00200000. To avoid conflict with SRAM map for > > PM, change them to 0x00210000 in the AT91Bootstrap via setting the CAN > > Memories Address-based Register(SFR_CAN) of SFR. > > > > Signed-off-by: Wenyou Yang <[email protected]> > > Tested-by: Quentin Schulz <[email protected]> > > --- > > The patch is tested on SAMA5D2 Xplained and based on the patch set, > > 1. [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1 > > http://marc.info/?l=linux-can&m=149165343604033&w=2 > > > > Changes in v3: > > - Add Tested-by tag. > > - Change the number of Rx Rx Buffers, Tx Buffers and Tx Event FIFO > > to maximum. > > > > Changes in v2: > > - Configures 10 TX Event FIFO elements and 10 TX Buffers/FIFO slots, > > because the TXE FIFO is needed to be configured. > > - Configure the offset of Message RAM for CAN1 followed from CAN0's. > > > > arch/arm/boot/dts/at91-sama5d2_xplained.dts | 24 +++++++++++++ > > arch/arm/boot/dts/sama5d2.dtsi | 56 > +++++++++++++++++++++++++++++ > > 2 files changed, 80 insertions(+) > > > > It didn't apply cleanly, can you please verify > https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git/log/?h=at91-dt
Verified, it works. Thank you for your effort. BTW, it will be better take the patch to add the config. [PATCH v2] ARM: at91/defconfig: add MCAN driver to sama5_defconfig I just submitted. > > -- > Alexandre Belloni, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com Best Regards, Wenyou Yang
