[PATCH v3 9/9] ARM: dts: imx6ul-isiot: Add FEC node support

[Jagan Teki]

From: Jagan Teki <ja...@amarulasolutions.com>

Add support for fec1 node on Engicam Is.IoT variant boards.

Cc: Shawn Guo <shawn...@kernel.org>
Cc: Matteo Lisi <matteo.l...@engicam.com>
Cc: Michael Trimarchi <mich...@amarulasolutions.com>
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v3:
- none
Changes for v2:
- Newly added patch

 arch/arm/boot/dts/imx6ul-isiot.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi 
b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index 7e947e5..ccc5477 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -129,6 +129,24 @@
        status = "okay";
 };
 
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy0>;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+               };
+       };
+};
+
 &pwm8 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm8>;
@@ -159,6 +177,21 @@
 };
 
 &iomuxc {
+       pinctrl_enet1: enet1grp {
+               fsl,pins = <
+                       MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO    0x1b0b0
+                       MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC     0x1b0b0
+                       MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                       MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                       MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                       MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+                       MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10       0x1b0b0
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
-- 
1.9.1