Am 04.04.2017 um 17:40 schrieb Maxime Ripard: > On Mon, Apr 03, 2017 at 07:00:11PM +0200, Patrick Menschel wrote: >> The A10 SoC has an on-board CAN controller. >> This patch adds the device node. >> >> This patch is adapted from the description in >> Documentation/devicetree/bindings/net/can/sun4i_can.txt >> >> Signed-off-by: Patrick Menschel <[email protected]> >> --- >> arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi >> b/arch/arm/boot/dts/sun4i-a10.dtsi >> index ba20b48..7c559e7 100644 >> --- a/arch/arm/boot/dts/sun4i-a10.dtsi >> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi >> @@ -1313,6 +1313,14 @@ >> #size-cells = <0>; >> }; >> >> + can0: can@01c2bc00 { >> + compatible = "allwinner,sun4i-a10-can"; >> + reg = <0x01c2bc00 0x400>; >> + interrupts = <26>; >> + clocks = <&apb1_gates 4>; >> + status = "disabled"; >> + }; >> + > This wasn't ordered properly. Fixed and applied. > > Now that you mention it, ps20 and ps21 do not follow follow the rising address order.
uart7: serial@01c29c00 {
...
i2c0: i2c@01c2ac00 {
...
i2c1: i2c@01c2b000 {
...
i2c2: i2c@01c2b400 {
...
can0: can@01c2bc00 {
...
ps20: ps2@01c2a000 {
....
ps21: ps2@01c2a400 {
...
The correct order would be
uart7, ps20, ps21, i2c0, i2c1, i2c2, can0 .
I'll fix that in patch v4.
Thanks,
Patrick
smime.p7s
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