On Fri, Feb 24, 2017 at 03:54:02PM +0200, Stefan Kristiansson wrote: > On Fri, Feb 24, 2017 at 01:48:10PM +0100, Jonas Bonn wrote: > > On 02/24/2017 11:54 AM, Stefan Kristiansson wrote: > > >eOn Fri, Feb 24, 2017 at 10:57:19AM +0100, Jonas Bonn wrote: > > >>On 02/24/2017 05:32 AM, Stafford Horne wrote: > > >>>From: Stefan Kristiansson <stefan.kristians...@saunalahti.fi> > > >>> > > >>>This brings it inline with the other setup oprations done like the cache > > >>>enables _ic_enable and _dc_enable. Also, this is going to make it > > >>>easier to initialize additional cpu's when smp is introduced. > > >>This patch confuses me. The TLB flush is moved to a point after MMU's are > > >>enabled. The TLB flush should happen before enabling the MMU, shouldn't > > >>it? > > >> > > >It still happens before the MMUs are enabled, the patch only refactors the > > >code > > >out into a function that is called from the place where it was open coded > > >before. > > > > Right. What's the point of moving it then? > > > > As the commit message mentions, it's a preparation patch for initialisation > of secondary cpus, which also will call this function. > > Perhaps this patch should be bundled with those patches. >
Thanks for replying on this patch, I think keeping this patch here is ok. Since part of the theme of this series is preparing for SMP (which will be another big series) I think its ok have any non SMP specific work into here. Its going to make my life a bit easier going forward. Also, as this is good refactor to get it structurally in sync with other initializations I think its not completely out of place. -Stafford
