Commit-ID: 08b259631b5a1d912af4832847b5642f377d9101
Gitweb: http://git.kernel.org/tip/08b259631b5a1d912af4832847b5642f377d9101
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Sun, 5 Feb 2017 11:50:22 +0100
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Sun, 5 Feb 2017 12:18:45 +0100
x86/CPU/AMD: Fix Zen SMT topology
After:
a33d331761bc ("x86/CPU/AMD: Fix Bulldozer topology")
our SMT scheduling topology for Fam17h systems is broken, because
the ThreadId is included in the ApicId when SMT is enabled.
So, without further decoding cpu_core_id is unique for each thread
rather than the same for threads on the same core. This didn't affect
systems with SMT disabled. Make cpu_core_id be what it is defined to be.
Signed-off-by: Yazen Ghannam <yazen.ghan...@amd.com>
Signed-off-by: Borislav Petkov <b...@suse.de>
Cc: <sta...@vger.kernel.org> # 4.9
Cc: Linus Torvalds <torva...@linux-foundation.org>
Cc: Peter Zijlstra <pet...@infradead.org>
Cc: Thomas Gleixner <t...@linutronix.de>
Link: http://lkml.kernel.org/r/20170205105022.8705-2...@alien8.de
Signed-off-by: Ingo Molnar <mi...@kernel.org>
---
arch/x86/kernel/cpu/amd.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 20dc44d..2b4cf04 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -319,6 +319,13 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
if (c->x86 == 0x15)
c->cu_id = ebx & 0xff;
+ if (c->x86 >= 0x17) {
+ c->cpu_core_id = ebx & 0xff;
+
+ if (smp_num_siblings > 1)
+ c->x86_max_cores /= smp_num_siblings;
+ }
+
/*
* We may have multiple LLCs if L3 caches exist, so check if we
* have an L3 cache by looking at the L3 cache CPUID leaf.
