On Fri, Dec 16, 2016 at 12:47 AM, Thomas Gleixner <t...@linutronix.de> wrote:
> On Thu, 15 Dec 2016, Andy Lutomirski wrote:
>> On Thu, Dec 15, 2016 at 8:44 AM, Thomas Gleixner <t...@linutronix.de> wrote:
>> > +static inline void toggle_debugctlmsr(unsigned long mask)
>> > +{
>> > + unsigned long msrval;
>> > +
>> > +#ifndef CONFIG_X86_DEBUGCTLMSR
>> > + if (boot_cpu_data.x86 < 6)
>> > + return;
>> > +#endif
>> > + rdmsrl(MSR_IA32_DEBUGCTLMSR, msrval);
>> > + wrmsrl(MSR_IA32_DEBUGCTLMSR, msrval ^ mask);
>> > +}
>> > +
>>
>> This scares me. If the MSR ever gets out of sync with the TI flag,
>> this will malfunction. And IIRC the MSR is highly magical and the CPU
>> clears it all by itself under a variety of not-so-well documented
>> circumstances.
>
> If that is true, then the code today is broken as well, when the flag has
> been cleared and both prev and next have the flag set. Then it won't be
> updated for the next task.
>
> The we should not use the TIF flag and store a debugmask in thread info and
> do:
>
> if (prev->debugmask || next->debugmask) {
> if (static_cpu_has(X86_FEATURE_BLOCKSTEP)) {
> rdmsrl(MSR_IA32_DEBUGCTLMSR, msrval);
> msrval &= DEBUGCTLMSR_BTF;
> msrval |= next->debugmask;
> }
> }
Seems reasonable to me. Although keeping it in flags might simplify
the logic a bit. FWIW, I doubt we care about performance much when
either prev or next has the bit set.
--Andy
