On Mon, Oct 10, 2016 at 11:55:45AM -0700, Luck, Tony wrote:
> How about this (this diff on top of current series, but obviously we'll
> fold it into part 07.
>
>
> commit cdb05159fb91ed1f85c950c0f2c6de25f143961d
> Author: Tony Luck <tony.l...@intel.com>
> Date: Mon Oct 10 11:48:42 2016 -0700
>
> Update the HSW probe code - better comments, and use IA32_L3_CBM_BASE
> as the probe MSR instead of PQR_ASSOC at suggestion of h/w architect).
>
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> index 4903e21d660d..e3c397306f1a 100644
> --- a/arch/x86/kernel/cpu/intel_rdt.c
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -56,39 +56,39 @@ struct rdt_resource rdt_resources_all[] = {
>
> /*
> * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
> - * as it does not have CPUID enumeration support for Cache allocation.
> + * as they do not have CPUID enumeration support for Cache allocation.
> + * The check for Vendor/Family/Model is not enough to guarantee that
> + * the MSRs won't #GP fault because only the following SKUs support
> + * CAT:
> + * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
> + * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
> + * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
> + * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
> + * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
> *
> - * Probes by writing to the high 32 bits(CLOSid) of the IA32_PQR_MSR and
> - * testing if the bits stick. Max CLOSids is always 4 and max cbm length
> + * Probe by trying to write the first of the L3 cach mask registers
> + * and checking that the bits stick. Max CLOSids is always 4 and max cbm
> length
I wonder what's worse - comparing SKU strings - we know that from the MCE
recovery experience - or poking at maybe nonexistent MSRs? :-)
I guess the latter is cleaner so let's try it.
Thanks for the writeup in the comments - this is exactly what I was
thinking about!
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284
(AG Nürnberg)
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