On 07/09/16 11:47, Dawei Chien wrote:
On Tue, 2016-09-06 at 11:28 +0800, Dawei Chien wrote:
Dear Rui,
On Tue, 2016-09-06 at 08:30 +0800, Zhang Rui wrote:
On 二, 2016-09-06 at 08:24 +0800, Zhang Rui wrote:
On 四, 2016-08-18 at 11:50 +0800, Dawei Chien wrote:
This adds the thermal controller and auxadc nodes
to the Mediatek MT2701 dtsi file.
Signed-off-by: Dawei Chien <dawei.ch...@mediatek.com>
---
This patch depned on:
https://patchwork.kernel.org/patch/9249589/
https://patchwork.kernel.org/patch/9249589/
Hmm, does this mean that I should take all these three patches and
hold
the patches in next merge window until the above patch has been
merged?
Yes, this patch is base on auxadc patchset.
Patch 3/3 can not be applied on top of upstream kernel, so I guess it
still has some other dependencies.
I think I can apply patch 1, 2 first. And patch 3/3 should be handled
in the dt tree.
Sorry, this patch is also need Mediatek's clock patchset what I miss to
add in dependency list, I would resend this dt tree once clock patch
merge, or resend this for right dependency on next version, thank you.
Actually, since patch1/patch2 would be OK so far, I would just only
resend patch3 after MTK clock pathcset ready, I prefer to merge
patch1/patch2 if possible, thank you.
From my side that's ok.
Regards,
Matthias
thanks,
rui
thanks,
rui
---
arch/arm/boot/dts/mt2701.dtsi | 44
+++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi
b/arch/arm/boot/dts/mt2701.dtsi
index e9150a4..cee4724 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -87,6 +87,36 @@
clock-output-names = "rtc32k";
};
+ thermal-zones {
+ cpu_thermal: cpu_thermal {
+ polling-delay-passive = <1000>; /*
milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&thermal 0>;
+ sustainable-power = <1000>;
+
+ trips {
+ threshold: trip-point@0 {
+ temperature = <68000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point@1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit@0 {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
@@ -222,4 +252,18 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+ thermal: thermal@1100b000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "mediatek,mt2701-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg
CLK_PERI_AUXADC>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg 0x10>;
+ reset-names = "therm";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
+
};
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