Hi Jeff-
> Also, should we be setting PCI_CACHE_LINE_SIZE for PCI devices as well
> as bridges?
If/when we do set PCI_CACHE_LINE_SIZE, please don't
set it to a hard-coded, inline constant, like 8 (e.g.),
like some drivers do.
Please use something like (PCI_CACHE_LINE_SIZE / 4)
instead. ["/ 4" to convert bytes to "dwords" or
whatever, since the PCI_CACHE_LINE_SIZE register
is in 4-byte units.]
~Randy
_______________________________________________
|randy.dunlap_at_intel.com 503-677-5408|
|NOTE: Any views presented here are mine alone|
|& may not represent the views of my employer.|
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