[Patch v3 07/11] driver/edac/fsl_ddr: Add DDR4 type

[York Sun]

Signed-off-by: York Sun <york....@nxp.com>

---
Change log
  v3: no change
  v2: no change

 drivers/edac/fsl_ddr_edac.c | 12 ++++++++++--
 drivers/edac/fsl_ddr_edac.h |  1 +
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 60761c0..88ecf7d 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -376,6 +376,9 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
                case DSC_SDTYPE_DDR3:
                        mtype = MEM_RDDR3;
                        break;
+               case DSC_SDTYPE_DDR4:
+                       mtype = MEM_RDDR4;
+                       break;
                default:
                        mtype = MEM_UNKNOWN;
                        break;
@@ -391,6 +394,9 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
                case DSC_SDTYPE_DDR3:
                        mtype = MEM_DDR3;
                        break;
+               case DSC_SDTYPE_DDR4:
+                       mtype = MEM_DDR4;
+                       break;
                default:
                        mtype = MEM_UNKNOWN;
                        break;
@@ -495,8 +501,10 @@ int fsl_ddr_mc_err_probe(struct platform_device *op)
        }
 
        edac_dbg(3, "init mci\n");
-       mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
-           MEM_FLAG_DDR | MEM_FLAG_DDR2;
+       mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
+                        MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
+                        MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
+                        MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
        mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
        mci->edac_cap = EDAC_FLAG_SECDED;
        mci->mod_name = EDAC_MOD_STR;
diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h
index 556bac5..c7b7dbf 100644
--- a/drivers/edac/fsl_ddr_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -50,6 +50,7 @@
 #define DSC_SDTYPE_DDR         0x02000000
 #define DSC_SDTYPE_DDR2                0x03000000
 #define DSC_SDTYPE_DDR3                0x07000000
+#define DSC_SDTYPE_DDR4                0x05000000
 #define DSC_X32_EN     0x00000020
 
 /* Err_Int_En */
-- 
2.7.4