Hi Xing, Am Dienstag, 2. August 2016, 15:19:56 schrieb Xing Zheng: > Export these source clocks for usbphy. > > Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
can you please provide a rationale why you need manual control over that intermediate clock? The two usbphys seem to use the clk_usb2phyX_ref clocks, generate the 480m clocks, but do not seem to need the clk_usbphyX_480m_src gates. The clk_usbphyX_480m_src clocks on the other hand only lead to the clk_usbphy_480m mux, so I'd like some explanation on what you want to achieve here :-) Thanks Heiko
