Zwane Mwaikambo <[EMAIL PROTECTED]> writes: > > The 7500 issue isn't actually a race but a disease, if you mask a pending > irq in its RTE, the PCI hub generates an INTx message corresponding to > that irq. This apparently was done to support booting OSes without APIC > support. So the following would occur; > > - irqN pending on IOAPIC > - mask > => INTx message for irqN > > Unfortunately it appears the below code would also be affected by this as > well, the appropriate reference is; > > 2.15.2 PCI Express* Legacy INTx Support and Boot Interrupt > http://download.intel.com/design/chipsets/datashts/30262802.pdf
Ouch. And this kind of thing isn't exactly uncommon. However if we have the irqs also disabled in the i8259 we should be safe from actually receiving this interrupt (even if it generates bus traffic), and when we enable the irq since it is level triggered we should still get an interrupt message. It isn't immediately obvious where the i8259 irq enable/disable happens. So i"m having trouble auditing that bit of code. Plus we can get very strange things like the irq number changing and the sharing rules being different when going through the i8259. So irqN may be irqM when going through the i8259. As long as we aren't using anything on the i8259 including the timer in ExtINT mode we can disable every interrupt pin and not worry about interrupts from that source. Eric - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
