On 11/07/16 10:33, Bharat Kumar Gogada wrote:
> Hi Marc,
>
> Thanks for the reply.
>
> From PCIe Spec:
> MSI Enable Bit:
> If 1 and the MSI-X Enable bit in the MSI-X Message
> Control register (see Section 6.8.2.3) is 0, the
> function is permitted to use MSI to request service
> and is prohibited from using its INTx# pin.
>
> From Endpoint perspective, MSI Enable = 1 indicates MSI can be used which
> means MSI address and data fields are available/programmed.
>
> In our SoC whenever MSI Enable goes from 0 --> 1 the hardware latches onto
> MSI address and MSI data values.
>
> With current MSI implementation in kernel, our SoC is latching on to
> incorrect address and data values, as address/data
> are updated much later than MSI Enable bit.
As a side question, how does setting the affinity work on this end-point
if this involves changing the address programmed in the MSI registers?
Do you expect the enabled bit to be toggled to around the write?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
