On Tue, Jun 21, 2016 at 7:10 AM, Tan Jui Nee <jui.nee....@intel.com> wrote:
> This driver uses the P2SB hide/unhide mechanism cooperatively > to pass the PCI BAR address to the gpio platform driver. > > Signed-off-by: Tan Jui Nee <jui.nee....@intel.com> > --- > Changes in V4: > - Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from > [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge > support driver for Intel SOC's > to > [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO > pinctrl in non-ACPI system > since the config is used in latter patch. > - Select CONFIG_P2SB when CONFIG_LPC_ICH is enabled. > - Remove #ifdef CONFIG_X86_INTEL_NON_ACPI and use > #if defined(CONFIG_X86_INTEL_NON_ACPI) when lpc_ich_misc is called > as suggested by Lee Jones. > - Use single dimensional array instead of 2D array for apl_gpio_io_res > structure and use DEFINE_RES_IRQ for its IRQ resource. I guess this patch will also change, also fix the screamings from the build robot please. Yours, Linus Walleij
