On Jun 4, 2016 1:53 PM, "Dan Williams" <dan.j.willi...@intel.com> wrote: > > Platforms supporting NVDIMMs are now required to provide persistence > guarantees once pmem stores are accepted by the memory subsystem.
Can you point us to a precise definition of what exactly constitutes stores being "accepted by the memory subsystem"? Back when pcommit was a thing (hah!), it was precisely documented in the SDM. > is usually achieved by a platform-level feature known as ADR > (Asynchronous DRAM Refresh) that flushes any memory subsystem write > pending queues on power loss/shutdown. Blech. Does this mean that we need some NMI handler or similar that does wbinvd? Will CPU caches automatically write themselves back on power loss? Will we lose data if something goes wrong with an SMI handler? > > The 'pcommit' instruction (which has not shipped on any product) is no > longer needed and is deprecated. Does this mean it will never ship? --Andy
