> On 27.04.2016, at 15:26, Matthias Reichl <h...@horus.com> wrote: > > dmaengine_pcm currently only supports setups where FIFO reads/writes > correspond to exactly one sample, eg 16-bit sample data is transferred > via 16-bit FIFO accesses, 32-bit data via 32-bit accesses. > > This patch adds support for setups with fixed width FIFOs where > multiple samples are packed into a larger word. > > For example setups with a 32-bit wide FIFO register that expect > 16-bit sample transfers to be done with the left+right sample data > packed into a 32-bit word. > > Support for packed transfers is controlled via the > SND_DMAENGINE_PCM_DAI_FLAG_PACK flag in snd_dmaengine_dai_dma_data.flags > > If this flag is set dmaengine_pcm doesn't put any restriction on the > supported formats and sets the DMA transfer width to undefined. > > This means control over the constraints is now transferred to the DAI > driver and it's responsible to provide proper configuration and > check for possible corner cases that aren't handled by the ALSA core. > > Signed-off-by: Matthias Reichl <h...@horus.com>
Tested-by: Martin Sperl <ker...@martin.sperl.org>
