Hi, On 27.04.2016 15:18, Elad Kanfi wrote:
From: Elad Kanfi <elad...@mellanox.com>Below is a description of a possible problematic sequence. CPU-A is sending a frame and CPU-B handles the interrupt that indicates the frame was sent. CPU-B reads an invalid value of tx_packet_sent. CPU-A CPU-B ----- ----- nps_enet_send_frame . . tx_packet_sent = true order HW to start tx . . HW complete tx ------> get tx complete interrupt . . if(tx_packet_sent == true) end memory transaction (tx_packet_sent actually written) Problem solution: Add a memory barrier after setting tx_packet_sent, in order to make sure that it is written before the packet is sent.
Should not those SMP memory barriers be paired? AFAIK you do not only have to make sure that the value written by CPU-A actually is written to memory but also that CPU-B reads that value from memory. At least this is what I have understood from memory-barriers.txt... Regards, Lino
