On Sat, 2016-03-26 at 20:47 +0200, Vladimir Zapolskiy wrote:
> The list of CPU model specific registers contains two copies of TDP
> registers, remove the one, which is out of numerical order in the
> list.
>
Thanks for finding this.
> Fixes: 6a35fc2d6c22 ("cpufreq: intel_pstate: get P1 from TAR when
> available")
> Signed-off-by: Vladimir Zapolskiy <vladimir_zapols...@mentor.com>
Reviewed-by: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com>
> ---
> arch/x86/include/asm/msr-index.h | 8 +-------
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index 2da46ac..426e946 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -190,6 +190,7 @@
> #define MSR_PP1_ENERGY_STATUS 0x00000641
> #define MSR_PP1_POLICY 0x00000642
>
> +/* Config TDP MSRs */
> #define MSR_CONFIG_TDP_NOMINAL 0x00000648
> #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
> #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
> @@ -210,13 +211,6 @@
> #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
> #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
>
> -/* Config TDP MSRs */
> -#define MSR_CONFIG_TDP_NOMINAL 0x00000648
> -#define MSR_CONFIG_TDP_LEVEL1 0x00000649
> -#define MSR_CONFIG_TDP_LEVEL2 0x0000064A
> -#define MSR_CONFIG_TDP_CONTROL 0x0000064B
> -#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
> -
> /* Hardware P state interface */
> #define MSR_PPERF 0x0000064e
> #define MSR_PERF_LIMIT_REASONS 0x0000064f
