* Mathieu Desnoyers ([EMAIL PROTECTED]) wrote: > > So it is "one cpu may write, other cpus may read", and as big as > > long. Are you sure obscure architectures (sparc?) can implement this > > in useful way? ... maybe yes, unless obscure architecture exists where > > second other cpu can see garbage data when first cpu writes into long > > ...? > > > > > > Sparc64 uses a memory barrier around the atomic operations in the SMP case > (see arch/sparc64/lib/atomic.S). The same is true for sparc. As I am not a > sparc > expert, I left the asm-generic default behavior, but I think it should be safe > to implement local.S code derived from atomic.S to optimize the speed of the > local_t operations on sparc and sparc64. Can anyone confirm this ? >
Sorry for the self reply.. looking at arch/sparc/lib/atomic32.c tells me that local.h could use its own version that would only disable interrupts without taking any hashed spinlock. sparc64 seems to be a saner architecture providing atomic operations wrt the local CPU. A barrier-free version of arch/sparc64/lib/atomic.S would improve performance. Mathieu -- OpenPGP public key: http://krystal.dyndns.org:8080/key/compudj.gpg Key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68 - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
